gate current
英 [ɡeɪt ˈkʌrənt]
美 [ɡeɪt ˈkɜːrənt]
网络 门电流; 栅电流; 闸极电流
双语例句
- The thyristor can be trigged into the on-state by applying a pulse of positive gate current for a short duration provided that the device is in its forward blocking state.
如果是处于正向阻断状态，只要在门极提供一个短暂的正脉冲，晶闸管就会导通。 - In general, for small-size device, effects of oxygen vacancy on gate leakage current should be considered.
栅漏电流随氧化层厚度的减小而增大，因此，在小尺寸器件中，必须考虑氧空位对栅漏电流的影响。 - However, when oxide thickness increased to a fixed value at a specific oxide field, the increase in gate leakage current caused by a single oxygen vacancy could be neglected.
但当厚度在特定值及特定电场下时，单个氧空位引起的栅漏电流增加可以忽略。 - The improvements are most likely due to the reduction of the gate leakage current and the charge injection effect.
这些效能改进的原因可以归之于经过表面处理后，闸极漏电流的降低以及载子注入的减少。 - But it provides too small emission current density and gives a large gate current.
但不足之处是发射电流密度太小和有较大的栅极电流。 - The gate current is produced by the tunneling, the electron surmounting and percolation.
发现器件的栅电流不是由单一的隧穿引起，同时还有电子的翻越和渗透。 - We use a quantum model based on self-consistent solutions to the Schro ¨ dinger-Poisson equations to investigate the reduction of gate tunneling current for nanoscale MOSFETs with different high-k materials and structures. The three-dimensional gate current component evaluation is performed by the traveling wave calculations.
采用Schro¨dinger-Poisson方程自洽全量子求解法研究了MOS器件不同介质材料和栅结构栅电流，该模型对栅电流中的三维电流成分用行波统一地计算； - A hot carrier injection degradation model for a DSM ( deep submicron) pMOS device is studied, which is based on the physical model of a degradation gate current.
研究了一种建立在退化栅电流物理解析模型基础上的深亚微米pMOS器件HCI（hotcarrierinjection）退化模型。 - A New Direct Tunneling Gate Current Model for Short Channel MOSFETs with HALO Structure
一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型 - The paper gives the current and voltage waveforms of multi GTO devices at turn-off, analyzes and compares the waveforms of gate current and voltage.
给出了多个GTO元件关断时的电流、电压波形.并对其门极电流、电压波形进行了分析和比较。 - Parameter Setup and PSpice Simulation for Linear AND-OR Gate with Base Current Source
有源馈电线性与或门的参数设置与PSpice模拟 - Experiment results show that no damage antenna scale dependent is found in Vt shift while corresponding plasma charging damage is detected in gate leakage current Ig, leak and sub-threshold characteristics at low drain electric field in nMOS devices of different antenna ratio ( AR).
试验结果表明在阈值Vt漂移中没有发现与天线尺寸相关的损伤，而在栅隧穿漏电流和低源漏电场下亚阈值特性中发现了不同天线比的nMOS器件有相应的等离子充电损伤。 - It's observed that three obvious spectrum peaks coexist in the proportional differential spectroscopy of direct tunneling gate current.
实验结果发现超薄栅氧化层直接隧道栅电流的比例差分谱存在明显的三个谱峰。 - A model for capacitance calculation is presented, in which the effects of gate contact leakage current is taken into account. Schottky diodes with the same structure but different leakages are analyzed with this model.
构造了考虑栅结漏电流影响的平面肖特基二极管电容计算模型，并用此模型对同一结构不同漏电流的肖特基二极管作了计算分析。 - The gate current produced by hot carriers are discussed in detail.
本文给出了LADES7软件模拟的部分结果，并着重讨论了热载流子效应产生的栅电流。 - However, the increment of gate leakage current increases abruptly after the soft breakdown.
但是，在软击穿时栅漏电流突然有大量的增加。 - Reduction of Gate Current in Nanoscale MOS Devices
减少纳米MOS器件栅电流的研究分析 - Gate Current Simulation of SOI LDD MOSFET
SOILDDMOSFET的栅电流的模拟 - The degradation of drain leakage current can be divided into two phases. Sub-threshold current is predominant in the first phase, while in the second phase gate current is predominant.
关态漏泄漏电流的退化分两个阶段：第一阶段亚阈值电流是主要成分，第二阶段栅电流是主要成分。 - The growth laws of hot carrier damage of PMOSFET's during the hot carrier degradation and the high field annealing are studied by direct gate current measurement.
通过直接栅电流测量方法研究了热载流子退化和高栅压退火过程中PMOSFET's热载流子损伤的生长规律。 - Hot-Carrier Damage of PMOSFET's Identified by Direct Gate Current Measurement
通过直接栅电流测量研究PMOSFET's热载流子损伤 - Gate Current for MOSFETs with High k Dielectric Materials Theoretical Modeling of Gate Current Distribution in MOSFET
高k栅介质MOSFET的栅电流模型（英文）MOSFET栅电流分布的理论建模 - These trapped holes may recombine with electrons tunneling into gate oxide due to the ultrathin gate oxide, and then many neutral electron traps would be generated and the gate oxide current would be increased.
由于栅氧化层很薄，陷落的空穴会与隧穿入氧化层中的电子复合形成大量中性电子陷阱，使得栅隧穿电流不断增大。 - By analyzing this model, the relationship between gate voltage and leakage current in different conditions has been discussed.
通过分析模型，讨论了不同条件下栅极电压与漏电流之间的关系。 - To a certain extent in reducing the size, MOSFET will reach the physical limits, and severe short channel effects and gate leakage current will appear.
在缩小到一定程度将达到它的物理极限，严重的短沟道效应和栅极泄漏电流将会出现。 - The mechanism and situation of the gate leakage current in small-scale MOS device were analyzed. Thus the influences of oxygen vacancy with its position distribution being random on the gate leakage current were calculated.
本文在分析了小尺寸MOS器件栅漏电流的组成机制及现状的基础上，计算了在栅氧化层中随机分布的氧空位对栅漏电流的影响。 - Usually, a current pulse is applied to the gate for the measurement. A novel gate charge testing circuit is presented in this thesis. The influence of control signal on gate input current is eliminated for the control signal is input from the source of the MOSFET.
本文提出一种新型栅电荷测试电路，该测试电路使控制信号从MOSFET的源极输入，消除了控制信号对栅极输入电流的影响。 - Based oncarriers 'transfer vertically, combined with the main component of gate leakage current, the conclusion is obtained that the gate leakage current is mainly induced by carriers' gate tunneling and thermal emission.
基于载流子纵向输运机制，结合栅泄漏电流的主要构成，分析表明栅泄漏电流主要由载流子的栅隧穿和热发射引起。 - Then the electrical characteristics of Ge-MOS capacitor with E-beam evaporation and magnetron sputtering are investigated. Experimental results show that the MOS devices fabricated by magnetron sputtering have better interface and gate leakage current properties.
通过对电子束蒸发和磁控溅射制备的La2O3/Ge-MOS电容电特性的研究，发现磁控溅射方法制备的器件有更好的界面特性和栅极漏电特性。 - DC gain is 80 dB, unity gain bandwidth is 100 KHz, and the phase margin is 90 °. Floating gate current source is introduced to make the circuit more compact. The area of this design is less than 600 100 square microns.
直流增益大于80dB，单位增益带宽积为100K，相位裕度为90°。浮栅电流源的引入使得本文设计的电路结构更紧凑，面积小于600100平方微米。